About Karl M. Guttag (KGOnTech)

Since 2011, the blog KGOnTech (www.kguttag.com) has analyzed consumer display devices and systems. The blog presents the technical analysis and opinions of Karl Guttag with 40 years of electronics industry experience in display devices, headset displays, projector displays, graphics accelerators, and video game devices.

Karl Guttag has 40 years of experience in Graphics and Image Processors, Digital Signal Processing (DSP), memory architecture, display devices (LCOS and DLP) and display systems including Heads Up Displays and Near Eye Display (augmented reality and virtual reality).   For the last 35 years was generally the lead technical person on the design and/or system product rising to TI Fellow at Texas Instruments and being the CTO at three startups.

Most recently he was CTO of Navdy a startup working on automotive heads up displays.   Prior Navdy he was the CTO of Syndiant developing LCOS used in projectors and head mount displays.  He has also provided technical expert support for I.P. litigation since 1999.

He is a named inventor on 150 issued U.S. Patents including key patents related to display devices, graphics/ imaging processors, graphics interface circuits, microprocessors, signal processing (DSP), Synchronous DRAMs, and Video/Graphics DRAM.  Billions of dollars of yearly revenue have been attributed to products using these inventions.

Expertise

  • Head Mount (Near-Eye) Displays
  • Microdisplay technology (LCOS, DLP, Laser Scanning)
  • Semiconductor Memory Architecture: SRAM, DRAM & VRAM, Video RAM, Graphics RAM, and Smart Memory architectures
  • Head Up Display for Automotive Use
  • Projector technology and applications
  • Graphics processors and graphics accelerators
  • Multimedia Processors and Multimedia Instruction Sets (SIMD Instructions)
  • Digital Signal Processors (DSP)
  • Microprocessor Design, Architecture, Logic, and Instruction Sets

Work Summary

Date:                2018-06 to present

Organization:    RAVN

Title:                 Cheif Science Officer

Summary:          RAVN is working on augmented reality headsets for military and first responder applications

Date:                2012-01 to present

Organization:    KGOnTech, Round Rock TX

Title:                 President

Summary:          KGOnTech provides independent technical and market consulting in the areas of display and graphics devices and systems.  KGOnTech also provides support for intellectual property (IP) litigation including being a technical expert, prior art research, and investigations of infringement.

A list of cases Karl Guttag has worked on since 2002 is included in Appendix A

Date:                2013-05 to 2015-01

Organization:    Navdy Inc, San Francisco CA

Title:                 CTO/CSO

Summary:          Navdy is a startup working on an aftermarket automotive Heads Up Display (HUD).  Navdy was selected as one of 11 of over 100 companies for the PCH International’s Highway1 Incubator.  The company is in the technology development stage of a high volume consumer device.   The company raise $6.5M product in 2014 and has over $3M in presales.

Date:                2004-12 to 2011-12

Organization:  Syndiant, Inc., Richardson, TX

Title:                 Founder and CTO

Summary:          Syndiant developed Liquid Crystal on Silicon (LCOS) display devices for pico projector applications and were based on his inventions.  Syndiant has the leadership position in high-resolution LCOS microdisplay for small (pico) projectors.  The devices have been designed into product marketed by 3M, Philips, and AAXA,  among others.  Syndiant’s devices and technology were being considered for integration into cell phones by a number of major companies.

As CTO he was the technical leader of the company.   He guided other senior engineers, help planned the roadmap for new devices, interfaced with engineers at customers and partner companies, and was the technical spokesperson for the company

Dates:               2001-07 to 2010-12

Organization:  Kagutech, Ltd.

Title:                 President

Summary:          For this intellectual property company, Mr. Guttag has invented and has issued Patents on new all-digital architectures for Microdisplay Backplanes.  The technology he invented at Kagutech by Karl Guttag was exclusively licensed to Syndiant.

Dates: 1998-05 to 2001-06

Organization:    Silicon Display Incorporated

Title:     CTO

Summary:          A startup company working on Liquid Crystal on Silicon for near eye and projector applications.  During that time Mr. Guttag was responsible for the architecture of a digital LCOS display device and the FPGA that interfaced to the display device as well as developing LCOS drive algorithms.

Dates:               1977-07 to 1998-05

Organization:    Texas Instruments (TI)

Titles:                TI Fellow (1988-1998), SMTS (1982-1988), Senior Engineer (1979-1982), Engineer (1977-1979)

Summary:          Most of his 20 years at TI was involved with the integrated circuits related to storing and manipulating graphics, imaging, and video data.  He was the lead integrated circuit architect of some of TI’s most advanced integrated circuits.

While at TI, he was the technical leader on a number of imaging and graphics related programs.  Mr. Guttag was the chief architect of the TMS320C8x (MVP) family (1990-1996) of image processors (which have been often cited in patent/legal procedures against Microunity patents) and the TMS340 family (1984-1989) of programmable graphics processors.

He led the definition of the first Video DRAM (VRAM) which today has become the Graphics DRAM or GDRAM.   He also was a significant contributor to the first Synchronous DRAM (SDRAM) that is used in the vast majority of computer systems.  He is a named inventor on key early patents related to both the early VRAM and SDRAM.

He led the definition of highly integrated Video Interface Palettes at TI (1984-1989) and other integrated circuits related to graphics systems including a floating point coprocessor for the TMS340 family.

He headed the logic and design architecture of the TMS 9995 (1979) and TMS 99000 (1980-1981) 16-bit microprocessors.  His work on these architectures plus his work on the VRAM, led to him being elected as the youngest Senior Member of Technical Staff (SMTS) in the history of TI in 1982.

In 1977 and 1978, he was one of the 6 original engineers on the TMS9918 “Sprite Chip” family (1977-1979) that was used in Colecovision, the Japanese MSX home computer, and TI’s 99/4 home computer.  This sprite architecture was later cloned and used by Nintendo in their game systems.  He directly worked on the Sprite architecture, DRAM interface definition, and logic verification of the TMS 9918 family (which included the 9918, 9918A, 9928, 9118, and 9128).

Litigation Support

Law Firm:Withheld
Disposition:Active
Date:2015-05-27 – ongoing
Case Name:Withheld
Provided:Technical consultant, gave Deposition
DispositionActive
  
Law Firm:Foley & Lardner LLP, Representing Renesas
Disposition:Settled
Date:2016-07-27 – 2016-08-07
Case Name:Advanced Silicon Technologies, LLC v. Renesas et al.,
Provided:Technical consultant, gave deposition on video
DispositionSettled
  
Law Firm:Covington & Burling LLP, Representing Texas Instruments Inc.
Disposition:Settled
Date:2016-03-30 – 2016-07-25
Case Name:Advanced Silicon Technologies, LLC v. Texas Instruments Incorporated et. al.
Provided:Technical consultant
DispositionSettled
  
Law Firm:O’Melveny & Myers LLP representing the defendant Samsung
Disposition:Case settled
Date:2011-03 – 2013-06
Case Name:Microunity v. Acer (Settled in 2010), Apple, AT&T, Google, HTC, LG Electronics, Motorola, Nokia, Qualcomm Samsung, Sprint and Texas Instruments (TI settled in 2013)
Services Provided:Technical consultant
Disposition:Case settled
Date:2011-03 – 2013-06
  
Law Firm:Baker Botts LLP representing the defendant Fusion-IO
Case Name:Solid State Storage Solutions v. STEC, OCZ Technology Group, Texas Memory Systems, Inc., PNY Technologies, Patriot Memory LLC, Fusion-IO, Other World Computing, Inc., and Mushkin, Inc.
Services Provided:Technical consultant
Disposition:Case settled with Fusion-IO
Date:2013-01 – 2013-02
  
Law Firm:Covington and Burlington representing the defendant Texas Instruments
Case Name:Microunity v. Acer (Settled in 2010), Apple, AT&T, Google, HTC, LG Electronics, Motorola, Nokia, Qualcomm Samsung, Sprint and Texas Instruments
Services Provided:Technical consultant
Disposition:Case settled with TI continuing with other defendants
Date:2010-09 – 2013-03
  
Law Firm:Covington and Burlington representing the defendant
Case Name:Graphics Properties Holdings, Inc v Research In Motion, HTC Corporation, LG Electronics, Inc, Apple Inc., Samsung Electronics Co., Sony Corporation, Sony Ericsson Mobile Communications, Motorola Mobility
Services Provided:Technical consultant including writing claim charts for invalidity and providing technical opinions about claim construction, non-infringement, and issues with the cited patents claims lack of enablement and being indefinite.
Disposition:Settled
Date:2012-05 – 2013-01
  
Law Firm:Quinn Emanuel Urquhart & Sullivan, LLP representing the defendant
Case Name:Intellectual Ventures I LLC, Intellectual Ventures II LLC  v. Hynix Semiconductor Inc., Hynix Semiconductor America Inc., Ellpida Memory, Inc. and Elipida Memory
Services Provided:Technical support in analyzing prior art and infringement claims including writing claim charts and writing documents related to non-infringement.
Disposition:Plaintiff dropped contentions against one of the patents for which Mr. Guttag generated the non-infringement arguments claim charts and soon after the case was settled.
Date:2012-06 – 2012-09
  
Law Firm:Finnegan, Henderson, Farabow, Garrett and Dunner L.L.P. representing the defendant
Case Name:Microunity v. Sony Entertainment
Services Provided:Technical consulting
Disposition:Settled before trial
Date:2007-09 through 2007-11
  
Law Firm:Latham & Watkins LLP representing the defendant
Case Name:St MicroElectronics v. Broadcomm
Services Provided:Technical consulting
Disposition:Settled before trial
Date:2003-05 through 2004-03
  
Law Firm:Munger, Tolles & Olson LLP representing the plaintiff
Case Name:Rambus v. N/A
Services Provided:Technical consulting
Disposition:Settled before trial
Date:2002-07 to 2002-10

Education

BSEE from Bradley University in 1976

MSEE from the University of Michigan 1977

Recognition

He was the youngest person elected to Senior Member of Technical staff after only 4.5 years at TI, and was the youngest person elected to TI Fellow at Texas Instruments, receiving this honor after less than 11 years after joining TI.  He was awarded the “Technical Achievement” award by the NCGA in 1988 for his work on the Video RAM.  At SID 2011 he won a Distinguished Paper Award for his paper on “Laser+LCOS Technology Revolution.”

Karl Guttag has been an invited speaker and has published numerous papers at many graphics, imaging, and integrated circuit conferences.   He has been regularly quoted in most of the major electronics and graphics magazines.

Publications

Karl Guttag has been an invited speaker and has published numerous papers at many graphics, imaging, and integrated circuit conferences over the last 36 years.   He has been regularly quoted in most of the major electronics and graphics magazines.  His recent publications include:

SID 2011: Distinguished Paper: Laser+LCOS Technology Revolution

SID Symposium Digest of Technical Papers — June 2011 — Volume 42, Issue 1, pp. 536-539

SID 2010: Invited Paper: High Resolution Microdisplays for Pico Projectors

SID Symposium Digest of Technical Papers — May 2010 — Volume 41, Issue 1, pp. 1057-1060

2nd International Symposium on Liquid Crystals: Science and Technology (LCST2011): Invited Paper: Digital High Resolution, Small Pixel LCOS Technology

IDW 2008 (Japan): 854 × 600 pixel LCOS microdisplay with 5.4 μm pixel pitch for pico-projectors: 195-198

IDW 2005 (Japan): A 1080p Digital LCOS Microdisplay Supporting Greater Than 12-bits per Color

IDW 2004 (Japan): Digital Microdisplay Backplane with Bit Serial SIMD Processing

PICOPROJECTION DISPLAYS: Laser-LCOS microdisplays make for tiny, low-cost picoprojectors, Laserfocusworld, volume-46, issue-1 January 2010

Projection Summit 2011: Projectors: Lasers are the Answer . . . Now what was the question? (presentation)

Projection Summit 2010: Why Resolution Matters (presentation)

Projection Summit 2009: How Can We Ship Over 100 Million Pico Projectors Per Year? (presentation)

Projection Summit 2007: Laser Illuminated Microdisplay Television

Interviews by Pico Projector Info 2009 though 2010:

http://www.picoprojector-info.com/syndiant-updates-interview-their-cto-karl-guttag

http://www.picoprojector-info.com/short-interview-syndiants-cto

http://www.picoprojector-info.com/interview-syndiants-co-founder-and-cto

Syndiant CTO Blog: http://syndiant.com/blog_CTO.html

KGOnTech Blog (current): https://www.kguttag.com

Seeking Alpha Contributing Author http://seekingalpha.com/author/karl-guttag/articles

Patents

To date, 150 U.S. patents have been issued with Karl Guttag as an inventor.  A number of the patents have been considered key patents in Texas Instruments’ patent portfolio and have resulted in significant licensing revenue to TI.  Most of these patents relate to digital signal processor architecture, graphics and imaging architectures, new DRAM architectures, and video.

Patent #Title
1. 8890903Spatial light modulator with storage reducer
2. 8766887Allocating registers on a spatial light modulator
3. 8605015Spatial light modulator with masking-comparators
4. 8558856Allocation registers on a spatial light modulator
5. RE44190Long instruction word controlling plural independent processor operations
6. 8,189,015Allocating memory on a spatial light modulator
7. 8,120,597Mapping pixel values
8. 8,089,431Instructions controlling light modulating elements
9. 8,035,627Bit serial control of light modulating elements
10. 8,004,505Variable storage of bits on a backplane
11. 7,924,274Masked write on an array of drive bits
12. 7,667,678Recursive feedback control of light modulating elements
13. 7,389,317Long instruction word controlling plural independent processor operations
14. 7,071,908Digital backplane
15. 7,039,795System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data
16. 6,948,050Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware
17. 6,829,696Data processing system with register store/load utilizing data packing/unpacking
18. 6,803,885Method and system for displaying information using a transportable display chip
19. 6,754,809Data processing apparatus with indirect register file access
20. 6,711,602Data processor with flexible multiply unit
21. 6,370,558Long instruction word controlling plural independent processor operations
22. 6,314,047Low cost alternative to large dual port RAM
23. 6,260,088Single integrated circuit embodying a risc processor and a digital signal processor
24. 6,240,437Long instruction word controlling plural independent processor operations
25. 6,232,955Palette devices, systems and methods for true color mode
26. 6,219,695Circuits, systems, and methods for communicating computer video output to a remote location
27. 6,219,688Method, apparatus and system for sum of plural absolute differences
28. 6,219,627Architecture of a chip having multiple processors and multiple memories
29. 6,173,394Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result
30. 6,116,768Three input arithmetic logic unit with barrel rotator
31. 6,098,163Three input arithmetic logic unit with shifter
32. 6,088,280High-speed memory arranged for operating synchronously with a microprocessor
33. 6,070,003System and method of memory access in apparatus having plural processors and plural memories
34. 6,058,473Memory store from a register pair conditional upon a selected status bit
35. 6,032,170Long instruction word controlling plural independent processor operations
36. 6,016,538Method, apparatus and system forming the sum of data in plural equal sections of a single data word
37. 5,995,748Three input arithmetic logic unit with shifter and/or mask generator
38. 5,995,747Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator
39. 5,982,694High speed memory arranged for operating synchronously with a microprocessor
40. 5,974,539Three input arithmetic logic unit with shifter and mask generator
41. 5,961,635Three input arithmetic logic unit with barrel rotator and mask generator
42. 5,960,193Apparatus and system for sum of plural absolute differences
43. 5,956,744Memory configuration cache with multilevel hierarchy least recently used cache entry replacement
44. 5,923,340Process of processing graphics data
45. 5,912,854Data processing system arranged for operating synchronously with a high speed memory
46. 5,808,958Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
47. 5,805,913Arithmetic logic unit with conditional register source selection
48. 5,768,609Reduced area of crossbar and method of operation
49. 5,761,726Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor
50. 5,742,538Long instruction word controlling plural independent processor operations
51. 5,734,880Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections
52. 5,727,225Method, apparatus and system forming the sum of data in plural equal sections of a single data word
53. 5,724,599Message passing and blast interrupt from processor
54. 5,712,999Address generator employing selective merge of two independent addresses
55. 5,701,507Architecture of a chip having multiple processors and multiple memories
56. 5,696,959Memory store from a selected one of a register pair conditional upon the state of a selected status bit
57. 5,696,954Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically ored with a third input logically ored with the sum/difference logically anded with an inverse of the third input
58. 5,696,913Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor
59. 5,694,348Method apparatus and system for correlation
60. 5,673,407Data processor having capability to perform both floating point operations and memory access in response to a single instruction
61. 5,651,127Guided transfers with variable stepping
62. 5,644,524Iterative division apparatus, system and method employing left most one’s detection and left most one’s detection with exclusive or
63. 5,640,578Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section
64. 5,634,065Three input arithmetic logic unit with controllable shifter and mask generator
65. 5,613,146Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors
66. 5,606,520Address generator with controllable modulo power of two addressing capability
67. 5,600,847Three input arithmetic logic unit with mask generator
68. 5,596,767Programmable data processing system and apparatus for executing both general purpose instructions and special purpose graphic instructions
69. 5,596,763Three input arithmetic logic unit forming mixed arithmetic and boolean combinations
70. 5,596,519Iterative division apparatus, system and method employing left most one’s detection and left most one’s detection with exclusive OR
71. 5,592,405Multiple operations employing divided arithmetic logic unit and multiple flags register
72. 5,590,350Three input arithmetic logic unit with mask generator
73. 5,587,954Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
74. 5,560,030Transfer processor with transparency
75. 5,537,563Devices, systems and methods for accessing data using a gun preferred data organization
76. 5,524,265Architecture of transfer processor
77. 5,522,083Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
78. 5,522,082Graphics display processor, a graphics display system and a method of processing graphics data with control signals connected to a central processing unit and graphics circuits
79. 5,517,609Graphics display system using tiles of data
80. 5,512,896Huffman encoding method, circuit and system employing most significant bit change for size detection
81. 5,509,129Long instruction word controlling plural independent processor operations
82. 5,493,646Pixel block transfer with transparency
83. 5,493,524Three input arithmetic logic unit employing carry propagate logic
84. 5,487,146Plural memory access address generation employing guide table entries forming linked list
85. 5,485,411Three input arithmetic logic unit forming the sum of a first input anded with a first boolean combination of a second input and a third input plus a second boolean combination of the second and third inputs
86. 5,479,166Huffman decoding method, circuit and system employing conditional subtraction for conversion of negative numbers
87. 5,471,592Multi-processor with crossbar link of processors and memories and method of operation
88. 5,465,224Three input arithmetic logic unit forming the sum of a first Boolean combination of first, second and third inputs plus a second Boolean combination of first, second and third inputs
89. 5,437,011Graphics computer system, a graphics system arrangement, a display system, a graphics processor and a method of processing graphic data
90. 5,434,969Video display system using memory with a register arranged to present an entire pixel at once to the display
91. 5,420,809Method of operating a data processing apparatus to compute correlation
92. RE34,881Graphics data processing apparatus having image operations with transparent color having selectable number of bits
93. 5,398,316Devices, systems and methods for accessing data using a pixel preferred data organization
94. 5,390,149System including a data processor, a synchronous dram, a peripheral device, and a system clock
95. 5,375,198Process for performing a windowing operation in an array move, a graphics computer system, a display system, a graphic processor and a graphics display system
96. 5,371,896Multi-processor having control over synchronization of processors in mind mode and method of operation
97. 5,371,517Video interface palette, systems and method
98. 5,333,261Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers
99. 5,327,159Packed bus selection of multiple pixel depths in palette devices, systems and methods
100. 5,317,333Graphics data processing apparatus with draw and advance operation
101. 5,309,551Devices, systems and methods for palette pass-through mode
102. 5,294,918Graphics processing apparatus having color expand operation for drawing color graphics from monochrome data
103. 5,293,468Controlled delay devices, systems and methods
104. 5,287,100Graphics systems, palettes and methods with combined video and shift clock control
105. 5,283,863Process for effecting an array move instruction, a graphics computer system, a display system, a graphics processor and graphics display system
106. 5,270,973Video random access memory having a split register and a multiplexer
107. 5,269,001Video graphics display memory swizzle logic circuit and method
108. 5,249,266Data processing apparatus with self-emulation capability
109. 5,239,654Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode
110. 5,231,694Graphics data processing apparatus having non-linear saturating operations on multibit color data
111. 5,226,125Switch matrix having integrated crosspoint logic and method of operation
112. 5,212,777Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
113. 5,185,859Graphics processor, a graphics computer system, and a process of masking selected bits
114. 5,163,024Video display system using memory with parallel and serial access employing serial shift registers selected by column address
115. 5,162,784Graphics data processing apparatus with draw and advance operation
116. 5,142,621Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers
117. 5,140,687Data processing apparatus with self-emulation capability
118. 5,095,301Graphics processing apparatus having color expand operation for drawing color graphics from monochrome data
119. 5,077,678Graphics data processor with window checking for determining whether a point is within a window
120. 5,056,041Data processing apparatus with improved bit masking capability
121. 4,933,878Graphics data processing apparatus having non-linear saturating operations on multibit color data
122. 4,825,390Color palette having repeat color data
123. 4,799,053Color palette having multiplexed color look up table loading
124. 4,752,893Graphics data processing apparatus having image operations with transparent color having a selectable number of bits
125. 4,747,081Video display system using memory with parallel and serial access employing serial shift registers selected by column address
126. 4,720,819Method and apparatus for clearing the memory of a video computer
127. 4,718,024Graphics data processing apparatus for graphic image operations upon data of independently selectable pitch
128. 4,694,391Compressed control decoder for microprocessor system
129. 4,688,197Control of data access to memory for improved video system
130. 4,663,735Random/serial access mode selection circuit for a video memory system
131. 4,660,156Video system with single memory space for instruction, program data and display data
132. 4,656,596Video memory controller
133. 4,648,077Video serial accessed memory with midline load
134. 4,639,890Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers
135. 4,603,381Use of implant process for programming ROM type processor for encryption
136. 4,590,552Security bit for designating the security status of information stored in a nonvolatile memory
137. 4,566,075Table lookup multiplier employing compressed data read only memory
138. 4,544,851Synchronizer circuit with dual input
139. 4,532,587Single chip processor connected to an external memory chip
140. 4,521,853Secure microprocessor/microcomputer with secured memory
141. 4,521,852Data processing device formed on a single semiconductor substrate having secure memory
142. 4,469,964Synchronizer circuit
143. 4,450,519Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
144. 4,434,462Off-chip access for psuedo-microprogramming in microprocessor
145. 4,422,143Microprocessor ALU with absolute value function
146. 4,403,284Microprocessor which detects leading 1 bit of instruction to obtain microcode entry point address
147. 4,402,044Microprocessor with strip layout of busses, ALU and registers
148. 4,402,043Microprocessor with compressed control ROM
149. 4,402,042Microprocessor system with instruction pre-fetch
150. 4,243,984Video display processor (original “Sprite-Chip” patent)

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